Input/output probing apparatus and input/output probing method using the same, and mixed emulation/simulation method based on it

ABSTRACT

An interactive environment is provided for integrated circuit (IC) designers to do an emulation session on a hardware accelerator  111  and then move to simulator  131 , and vice versa. An aspect of the present inventive solution swaps memory state and logic storage node state (such as flip-flops and latches) between the accelerator  111  and simulator  131 . A complete context switch is performed to create a time shared environment on hardware accelerator  111  so that multiple IC designers can access and use the accelerator. Multiple memory pages can be incorporated to minimize state swap time. Multiple accelerators  111  can be interconnected with a plurality of simulators  131  and a plurality of workstations  101  to allow multiple designers to do interactive operations and allows shifting back and forth between hardware emulation and software simulation.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a technique for verifying andinspecting a designed digital circuit, and more particularly to aninput/output probing apparatus which is capable of implementing adesigned digital circuit as a programmable chip or as an order-builttype semiconductor chip actually by hardware and capable of quicklyverifying and inspecting it on an emulation basis, and a method usingthe same. Further, the present invention relates to a mixedemulation/simulation method which is capable of implementing a designeddigital circuit as a programmable chip or as an ASIC semiconductor chipactually by hardware, capable of automatically switching from emulationto simulation executed by means of a simulator on a computer duringemulating process, or reversely, capable of automatically switching fromsimulation executed on the computer by the simulator to emulation,thereby performing emulation and simulation in turn more than one timefor verification and a mixed emulation/simulation verifying apparatustherefor.

2. Description of the Related Art

Recently, as a design for an integrated circuit and a semiconductorprocess technique are being rapidly developed, a design of a digitalcircuit tends to be enlarged and its construction becomes complicate.Accordingly, as competition in the market turns keen more and more, amethod for verifying a designed circuit quickly and effectively issought to meet the necessity.

Up to now, generally, a simulator, an approach based on software, hasbeen employed to verify a designed digital circuit. Thanks to itsadvantage of using various delay models for a circuit, thesimulation-based verifying method using the simulator allows a timingverification as well as a functional verification, and above all, itprovides a perfect visibility for every signal line existing in acircuit during debugging.

However, as for the simulator, since a software code consisting ofsequential instruction sequences, which is obtained by modeling thedesign verification circuit by software, is to be sequentially performedon computer, time for verification is taken for a long time, with alimitation that it fails to be integrated with a peripheral hardwareenvironment for In-Circuit Emulation (referred to as an ICE,hereinafter).

Moreover, referring to the verification through simulation, sinceperformance of a computer dependent on a simulation software and asingle processor fails to come up with the complexity of a digitalcircuit of tens of thousands of gates which are rapidly increased,recently, it incurs an extremely long time to perform a simulation for ageneral design verification.

Comparatively, a hardware emulation based design verification method,that actually implements a designed circuit as a chip to use it, isadvantageous in that since the digital circuit is verified while beingparallely operated, design verification can be possibly carried out at amillion time speed at the maximum compared to that of the simulation,and ICE environment is possibly constructed with respect to a peripheralhardware environment for integrated verification.

However, the emulation is not good for debugging compared to thesimulation. The reason for this is that the visibility showing logicvalues of numerous signal lines existing in the circuit implemented withprogrammable chips or ASIC chips is exorbitantly degraded compared tosimulation.

As a core device for emulation-based design verification, reusable fieldprogrammable devices (referred to as ‘RFPD’, hereinafter), that is,programmable chips, are employed. The RFPD includes a field programmablegate array and a complex programmable logic device. These days, withdevelopment of a semiconductor technique, the RFPD is highly integrated,making it possible to use a single RFPD or a very few RFPD for complexdigital circuits and prototype it.

Unlike the implementation of a circuit using the ASIC chip, in case thata circuit is implemented by using the RFPD, it is advantageous in thatit can be carried out in the field at a low cost, and time and expenseare considerably reduced to correct a bug as being found.

The feature of the present invention also can be applied to a case ofusing an ASIC chip using a technique such as a standard cell or to agate array in the same manner as well as the case of using the RFPD forimplementation of the design verification circuit, but in thedescription of the present invention, using of the RFPD is taken forexplanation's convenience.

As mentioned above, though prototyping can be economically performedowing to the development in the highly integrated semiconductortechnique, since the numerous signal lines on the digital circuit, thetarget for design verification in prototyping, mostly exist inside theRFPD, it is difficult to probe the signal lines, degrading visibilityfor debugging. This problem would be more serious in the future whenmore highly integrated RFPD is expected to be used.

In order to solve the problem, a method is required for performing aneffective and rapid probing even in the case that the signal lines ofthe circuit exist inside the chip, so that a circuit subjected to designverification as being implemented in the RFPD can be effectively andrapidly debugged.

Besides, in order to maximize the efficiency for design verification ofa digital circuit, a method of mixedly using emulation and simulationappropriately in turn during design verifying process is required.

That is, a high speed function verification is carried out to the pointof time when and in a specific situation where a very fineidentification is required on the emulation basis for designverification. Thereafter, the verifying method is automatically switchedfrom an emulation basis to a simulation basis to perform a functionalverification or a timing verification with a 100%-perfect visibility forthe target circuit of verification.

In this respect, switching between emulation and simulation is repeatedmore than one time, as necessary, to thereby maximize efficiency of theverification.

However, to date, in case that a hardware board (referred to as‘arbitrary prototyping board’, hereinafter) on which a digital circuitis implemented with the RFPD, the programmable chip, or with a generalASIC semiconductor chip, is subjected to a design verification on theemulation basis, no input/output probing apparatus using an openarchitecture that can perform debugging rapidly and effectively even fora hardware board, not limiting to a specific hardware board, and noinput/output probing method has been presented.

And, a general tendency shows that designers design a digital circuit byusing a gated clock or a locally generated clock, rather than designinga fully synchronous circuit, to reduce a power consumption or due tovarious reasons.

However, such asynchronous factors make input/output probing for acircuit, especially, an input probing, very difficult. In addition, noinput/output probing method has been proposed to cope with such ageneral situation.

Moreover, there has not been proposed any method and apparatus formixedly using emulation and simulation for verification to therebyremove the shortcomings of the emulation-based verification method, in amanner of employing the hardware board on which an arbitrary ASICsemiconductor is mounted that implements a circuit subjected to a designverification including the asynchronous factors and an arbitrarysimulator.

Especially, in case where simulation is first performed and emulation issubsequently performed, before emulation starts, memory devices andmemories which exist in a circuit implemented in the RFPD that performsemulation are to have the same logic values as the logic values at thecurrent time point of the memory devices (flipflops or latches) and thememories (RAM or ROM) of a design verification target circuit obtainedby simulation.

However, in preparation for an asychronous situation in which a gatedclock and a locally generated clock signal are applied to the clockinput of the memory devices existing in the design verification targetcircuit, no method has been proposed to freely replace the logic valuesof memory devices existing in the circuit implemented in the RFPD withthe specific logic values obtained by the result of simulation.

Furthermore, thanks to the recent development of the Internettechnology, a general tendency is that a designer, a software for adesign, a simulator, a hardware board for emulation, a server computerare dispersed and connected through network, rather than beingcollectively positioned in a place.

With such an environment in which the simulator and the hardware boardare separately positioned at a distance, no method has been proposed toperform emulation and simulation in turn at a high speed in atime-shared system for a single design verification target circuitthrough a local area network or a remote area network.

In addition, the above described technique may be applied not only to adesign verifying stage of a circuit but also to a testing stage afterthe circuit is completely fabricated.

A scan technique is one of the widely used technique to inspect thecircuit. However, the scan fails to provide any controllable method forthe memory devices using the gated clock or the locally generated clockas stated above.

The input/output probing method in accordance with the present inventionbasically provides a perfect controllability and an observability forany memory devices existing in a circuit, which, thus, is superior tothe scan method in the aspect of circuit inspecting.

U.S. Pat. No. 5,937,179 filed by Texas Instrument (TI) discloses amethod for performing emulation and simulation in turn. But it employsthe above mentioned scan chain, that is, a general technique for circuitinspecting, which is not able to control a circuit if the circuit wouldinclude a memory device that would use the gated clock or the locallygenerated clock.

That is, it has problems that the mixed emulation/simulation is notavailable to circuits having an asynchronous factor, and it is designedto be adopted only for the completely synchronous circuit in which thesame clocks are applied to the every memory device existing therein.Also, since it doesn't not have an open architecture, it is not possibleto be applied to a hardware board.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide a rapidinput/output probing apparatus and input/output probing method using thesame which are capable of enabling an input/output probing systemcontroller to add a supplementary circuit to a design verification orinspection target circuit to thereby automatically generate an extendedcircuit suitable for input/output probing so as to be implemented in asemiconductor chip, thereby performing an effective design verificationor inspection for a digital circuit.

Another object of the present invention is to provide an input/outputprobing method for mixedly performing emulation and simulation toperform input/output probing even for any prototyping board by means ofan input/output probing apparatus, thereby rapidly and effectivelydebugging.

To achieve these and other advantages and in accordance with the purposeof the present invention, as embodied and broadly described herein,there is provided an input/output probing apparatus including aninput/output probing system controller and an input/output probinginterface module.

The input/output probing system controller of the present inventionincludes an input/output probing system software, and the input/outputprobing interface module may include an interface module and aninterface cable.

The input/output probing system controller is executed in a servercomputer, and the server computer may includes a simulator or may beconnected with a different computer having a simulator through a remotelocal area network.

The input/output interface module serves to connected the servercomputer having the input/output probing system controller with aprototyping board including at least one semiconductor chip (i.e., FPGA)for implementing a designed digital circuit.

Another primary function of the input/output probing interface module isto generate at least one system clock and probing clock required forinput/output probing, an operating mode control signal, a probing modecontrol signal or a probing memory reading/writing signal under thecontrol of the input/output probing system controller and to supply themto the prototyping board as necessary, thereby controlling performingand stopping of the prototyping board.

For this purpose, the input/output probing interface module includes aFPGA or CPLD, microprocessor or a microcontroller, or a special ASICchip.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiments of the invention andtogether with the description serve to explain the principles of theinvention.

In the drawings:

FIG. 1 is a schematic view of an input/output probing apparatus inaccordance with the present invention;

FIG. 2 is a schematic view of one example of a shaft register arraystructure in which a parallel load and a serial load constructed as anIOP-probing supplementary circuit is available according to aninput/output mode in accordance with the present invention;

FIG. 3 is a schematic view of another example of a shaft register arraystructure in which a parallel load and a serial load of FIG. 2 isavailable according to an input/output mode in accordance with thepresent invention;

FIGS. 4A and 4B are schematic views showing a symbol and a functionalfunction of a single input D-type flipflop having a single data input(D) in accordance with the present invention;

FIGS. 4C and 4D are schematic views showing a symbol and a functionalfunction of a single input D-type flipflop having a single data input(D) and an asynchronous set/reset (AR/AS) in accordance with the presentinvention;

FIGS. 4E and 4F are schematic views showing a symbol and a functionalfunction of a dual-input D-type flipflop having two data inputs (D1, D2)in accordance with the present invention;

FIGS. 4G and 4H are schematic views showing a symbol and a functionalfunction of a dual-input D-type flipflop having two data inputs (D1, D2)and effective (EN) input in accordance with the present invention;

FIGS. 4I and 4J are schematic views showing a symbol and a functionalfunction of a D-type flipflop having a data input (D), an asynchronousset (AS) and an asynchronous reset (AR) and a synchronous effective (EN)input in accordance with the present invention;

FIG. 5 is an exemplary view of an asynchronous circuit, that is, a 4-bitasynchronous binary counter in accordance with the present invention;

FIG. 6 is a schematic view showing an example of implementation of thedual-input D-type flipflop of FIG. 4A in accordance with the presentinvention;

FIG. 7A is a schematic view showing a situation in which an IOP-probingsupplementary circuit is added to a design verification target circuitof FIG. 5 in accordance with the present invention;

FIG. 7B is a schematic view showing a control circuit in use for thesituation that the IOP-probing supplementary circuit has been added tothe design verification target circuit of FIG. 5 and defining it with atruth table in accordance with the present invention;

FIG. 7C is a schematic view showing another situation in which anIOP-probing supplementary circuit is added to a design verificationtarget circuit of FIG. 5 in accordance with the present invention;

FIG. 7D is a schematic view showing a control circuit in use for anothersituation that the IOP-probing supplementary circuit has been added tothe design verification target circuit of FIG. 5 and defining it with atruth table in accordance with the present invention;

FIG. 7E is a schematic view showing still another situation in which anIOP-probing supplementary circuit is added to a design verificationtarget circuit of FIG. 5 in accordance with the present invention;

FIG. 7F is a schematic view showing a control circuit in use for thestill another situation that the IOP-probing supplementary circuit hasbeen added to the design verification target circuit of FIG. 5 anddefining it with a truth table in accordance with the present invention;

FIG. 7G is a schematic view showing yet another situation in which anIOP-probing supplementary circuit is added to a design verificationtarget circuit of FIG. 5 in accordance with the present invention;

FIG. 7H is a schematic view showing a control circuit in use for the yetanother situation that the IOP-probing supplementary circuit has beenadded to the design verification target circuit of FIG. 5 and definingit with a truth table in accordance with the present invention;

FIG. 8A is a schematic view showing a situation in which a flipflop ofthe design verification target circuit has an asynchronous set and anasynchronous reset in accordance with the present invention.

FIG. 8B is a schematic view showing a situation in which the flipflop ofFIG. 8A is converted in an extended design verification target circuitin accordance with the present invention;

FIG. 8C is a view showing a truth table of the control circuit used inFIG. 8B in accordance with the present invention;

FIG. 8D is a schematic view showing a situation in which a flipflop ofthe design verification target circuit has an asynchronous set and anasynchronous reset in accordance with the present invention.

FIG. 8E is a schematic view showing a situation in which the flipflop ofFIG. 8D is converted in an extended design verification target circuitin accordance with the present invention;

FIG. 8F is a view showing a truth table of the control circuit used inFIG. 8E in accordance with the present invention;

FIG. 9 is a view showing a construction of a circuit functionallyequivalent to a latch with a flipflop and a multiplexer in accordancewith the present invention;

FIG. 10 is a schematic view showing an example of implementing a memoryprobing finite state machine as a supplementary circuit for probing amemory in accordance with the present invention;

FIG. 11 is a flow chart of an embodiment of input/output probing byusing the input/output probing apparatus of FIG. 1 in accordance withthe present invention;

FIG. 12 is a schematic view showing mixed emulation/simulationenvironment in accordance with the present invention;

FIG. 13 is a schematic view showing a construction of mixedemulation/simulation environment through a local/remote area network inaccordance with the present invention;

FIG. 14 is a schematic view showing a construction of mixedemulation/simulation environment through an inter-network in accordancewith the present invention;

FIG. 15 is a flow chart of a design verification method according to oneembodiment of the mixed emulation/simulation using FIGS. 12, 13 or 14 inaccordance with the present invention; and

FIG. 16 is a flow chart of a design verification method according toanother embodiment of the mixed emulation/simulation using FIGS. 12, 13or 14 in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A preferred embodiment of the present invention will be described below,with reference to the accompanying drawings.

FIG. 1 schematically shows a I/O (input/output) probing systemconsisting of a I/O probing system control unit operated under thecontrol of a computer used as a server and a I/O probing interfacemodule.

The I/O probing interface module 26 shown in FIG. 1 is typically mountedin a PCI (peripheral computer interface) slot to be connected to a PCIbus of the server computer 20 or a secondary system bus, such as S-busof SUN workstation, similar to the PCI bus. However, in case of highspeed applications, the module 26 may be connected to a main bus orprimary system bus of the server computer. If a low speed operation isallowed, the connection of the module 26 may be implemented using a USB(Universal Serial Bus), etc. through which the server computer 20 andany of prototyping boards 44 can be connected.

The I/O probing system control unit 32 can read from the prototypingboards the complete or partial state information relating to a designverification targeted circuit implemented on-any of the prototypingboards 44, at a time point or situation as desired by a user, andconversely the unit 32 can write specific state information into theboard.

To this end, a semiconductor chip mounted on any of the prototypingboards is required to have three physical pins for providing anoperational mode controlling (normal mode*/probing mode) signal, aprobing mode controlling (input probing*/output probing) signal and aprobing clock, and one or more I/O pins capable of providing I/O probingdata signals. In addition, a connector connected to those pins on theboard is provided so that the pins are connected to the I/O probinginterface module 26.

Also, in case of performing I/O probing of memories built in thesemiconductor chip, one additional physical pin serving as a probingmemory read/write (absent*/present) signal is required to be connectedto the I/O probing interface module 26.

It is noted that the term of state information means to represent valuesstored in memory components, such as a flip flop or a latch, of adigital circuit and the content stored in memories such as RAMs or ROMs.The complete state information means values stored in all memorycomponents and the whole content stored in all memories, and the partialstate information denotes values of some memory components and/orcontents of some memories included in the targeted circuits.

It is noted that the terms of the memory components and the memory areused in different meanings, respectively. The term of the memorycomponent is used to indicate a flip flop or a latch, while the term ofthe memory is used to indicate RAMs (random access memory) or ROMs (readonly memory).

A method for performing I/O probing for a circuit in which no memoriesare provided will be explained below, but a method for performing I/Oprobing for a circuit having memories will be explained thereafter.

An I/O probing system software in the I/O probing system control unit 32shown in FIG. 1 comprises an I/O probing circuit synthesizer thatgenerates automatic probing version of the designed circuit to beverified (the targeted circuit) so that I/O probing for the circuitbecomes possible. The I/O probing circuit synthesizer can generate acircuit completed in an automatic manner (which is hereinafter called“expanded verification target circuit”) by incorporating an additionalIOP-probing circuit to the verification targeted circuit.

In an output probing mode, the additional IOP-probing circuit furtherincluded in the expanded verification target circuit may be implementedby a shift register, and serves to apply logical values of all or someof memory components in the verification target circuit to the shiftregister, before its shifting operation clocked by the probing clock ismade.

In an input probing mode, the additional circuit implemented by theshift register also performs the shifting operation. Under the inputprobing mode, the additional circuit performs the shifting operation soas to apply input probing values to all or some of the memory componentsin the verification target circuit. The start-up operation of theadditional circuit is made by synchronous set or synchronous resetoperation, by synchronous set or synchronous reset operation subsequentto asynchronous set or asynchronous reset operation, or by synchronousdisable operation subsequent to asynchronous set or asynchronous resetoperation.

In the normal mode, another function of the additional IOP-probingcircuit is to provide a circuit by which functional logical behaviors ofthe verification target circuit remains still unchanged, even if theadditional circuit is added.

In case the verification target circuit is to be implemented using HDL(hardware description language) codes, the complete HDL codes areattained by adding the additional HDL codes expressing the behaviors ofthe additional IOP-probing circuit to the HLD codes for the verificationtargeted circuit.

Immediately before the shifting operation clocked by the probing clockis made, signal lines for register HDL codes holds output signals valuesfrom all or some of the memory components to be verified through theoutput probing.

Under the input probing mode, the HDL codes portions by the additionalHDL codes is of the shift register structure, and therefore performs theshifting operation clocked by the probing clock.

The input probing targeted signals of the HDL codes by such a shiftingoperation undergo synchronous set or synchronous reset operation,synchronous set or synchronous reset operation subsequent toasynchronous set or asynchronous reset operation, or synchronous disableoperation subsequent to asynchronous set or asynchronous resetoperation, whereby logical values of the input probing targeted signalsbecomes the input probing values.

In the normal mode operation, another function of the additionalIOP-probing HDL codes is to invariably maintain behaviors of the HDLcodes during verification included in the expanded verification HDLcodes, even if the additional HDL codes are added.

FIG. 2 schematically shows one example of a shift register arrayselectively providing parallel loading and serial loading operationsunder I/O mode settings, implemented by two-input D type flip flops 75and a tri-state buffer 79 to form the additional IOP-probing circuit.

FIG. 3 schematically shows another example of a shift register arrayformed using single input D type flip flops 76, a tri-state buffer 79and multiplexer 74.

FIG. 4 shows symbols representing various D type flip flops and thefunctions thereof, used in an additional IOP-probing circuit, includingthe shift register array.

FIG. 6 schematically shows an example which the dual input D type flipflops in FIG. 4 are implemented by multiplexer 74 and the signal input Dtype flip flop.9.

Assuming that a RFPD 12 is employed as a semiconductor chip used forimplementing the circuit, one approach to embody functions of theadditional IPO-probing circuit will be explained in detail.

The additional IOP-probing circuit may be implemented by one or moreshift register arrays capable of selectively providing parallel-loadingor serial-loading functions in response to a change in mode, whichfunction is accomplished by dual input flip-flops and signal lines fromthe memory components to be probed which are built in one or more RFPDchips.

In the output probing mode, each one input of the dual input flip flopis connected to the output signal line from the targeted memorycomponent so that the logical values on the output signal lines can beparallel loaded to the each of the flip flops. Thereafter, the outputfrom one flip flop in an each array of the one or more shift registersis logically connected to the I/O pins functioning as one or more outputprobing lines of the related RFPD, and, according to the shiftingoperation clocked by the probing clock, the logical values of all flipflops constituting the shift register are sequentially appeared on theI/O pins serving as the output probing lines.

In such an output probing mode, the targeted signal lines may be acandidate for the output lines of the memory components, but they may beused as the output lines of the combinational gates. In the inputprobing mode, the input probing action is taken only for the outputlines of the memory components so that the input probing values can bestored in the memory components. With such a configured shift registerarray, the output from one flip flop in an array of the one or moreshift registers that a serial load becomes possible is logicallyconnected to one of the I/O pins functioning as one or more inputprobing lines of the associated RFPD. Thereby, by the shifting operationclocked by the probing clock, the input probing values supplied from theexternal through the I/O pins functioning as the input probing lines canbe loaded to the shift register in a serial manner. Further, in case asystem clock (which means a clock globally used throughout the targetedcircuit) is directly connected to the clock input of the related memorycomponents to be input probed, each output of the flip flopsconstituting an array of the shift register that a serial load ispossible is connected one date input of the dual input flip flopreplacing each of the related memory components driving each of theinput probing target signal lines.

Meanwhile, in case of being not directly connected to the system clock,i.e. in case of using a gated clock or a clock locally generated, therespective memory components driving the respective input probing targetsignal lines are replaced with the dual input flip flops each havingasynchronous set and asynchronous reset. These asynchronous set andreset inputs are controlled by the output lines of the flip flops havingthe input probing values for the targeted memory components, theoperational mode controlling line, and output lines of a finite statemachine (FSM) for probing the memory components, thereby making itpossible asynchronous reset or asynchronous set of the memory componentsat specified time point. Also, the output line of the flip flop havingthe input probing values for the memory component are connected to onedata input of the dual input flip flop replacing the targeted memorycomponents of the user's circuit. Thus, by synchronous set orsynchronous reset subsequent to the asynchronous set or asynchronousreset, the outputs of the input probing target memory components cantake either of logical values “0” or “1” which the flip flop having theinput probing values for the memory components is holding.

Meanwhile, in case the clock inputs of the memory components are notdirectly connected to the system clock, as alternative method differentfrom the above described method, the respective memory componentsdriving the respective input probing target signal lines are replacedwith the flip flops each having asynchronous set, asynchronous reset andsynchronous enable. These asynchronous set and asynchronous reset inputsare controlled by the output lines of the flip flops, among the flipflops constituting an array of the shift register, having the inputprobing values for the targeted memory components, the operational modecontrolling line, and the output lines of the FSM for probing the memorycomponents, thereby making it possible asynchronous reset orasynchronous set of the memory components at specified time point. Also,another output lines of the FSM for the probing are connected thesynchronous enable of the flip flop replacing the memory components ofthe user's circuit to be input probed, so that the output of the inputprobing target memory components are set to have either of logicalvalues “0” or “1” which the flip flop having the input probing value forthe memory components is holding.

Rather than using the flip flops present in the targeted circuit,separate new flip flops can be employed as the flip flops used in anarray of the shift register providing the parallel and serial loadingaccording to the change in mode. Alternatively, some portions among theflip flops used in the shift register array may be selected from theflip flops constituting the targeted circuit, and the use of selectedflip flops may need the modification to further add, for example,synchronous enable and a multiplexer.

In case of the former, the advantage is that the minimal disturbance tothe targeted circuit is guaranteed during the input probing performance.In case of the latter, the advantage is that the minimal overhead forthe input probing is possible.

To attain such an input probing performance, it requires to additionallyhave the FSM for probing the memory components. It is noted that the FSMfunctions to create and provide the set/reset enable signal such thatthe asynchronous set or asynchronous reset occurs in the input probingtarget memory component by the signal values supplied from the shiftregister array, only at a time point as necessary, or functions toprovide, as the input data selection signal of the dual input flip flopsubsequent to the asynchronous set or asynchronous reset, thesynchronous set or synchronous reset to the dual input flip flop. Or,the FSM also functions to create and provide the set/reset enable signalsuch that the asynchronous set or asynchronous reset occurs in the inputprobing target memory component by the signal values supplied from theshift register array, only at a time point as necessary, or functions tocreate and provide the synchronous set or synchronous reset.

For this, the intended control for the asynchronous set and asynchronousreset of the input probing targeted memory components should be possibleusing the output lines of the flip flop of the shift register arrayhaving the input probing values for the targeted memory components, theset/reset enable signal lines from the FSM for probing the memorycomponents, and the operational mode controlling (normal mode*/probingmode) signal lines. This requirement can be attained by defining simplecombinational functions. Also, in case all or some of the memorycomponents used in the target circuit already have the asynchronous setand the asynchronous reset and the system clock is directly notconnected to the clock inputs of those memory components, it is notdifficult to try the modification of the circuit to the additionalIOP-probing circuit including the control circuit unit driving theasynchronous set and asynchronous reset inputs, by replacing the abovememory components to be input probed with the dual input flip flophaving the asynchronous set/reset, or a single input flip flop havingthe asynchronous set/reset and the synchronous enable, while thefunctional logical behavior of the original targeted circuit remainsunchanged in the normal mode.

FIG. 5 illustrates an implementation of the above example, showingfour-bit asynchronous binary counter consisting of D type flip flops 76and an inverter gate. The physical connection (which is contrasted withthe logical connection) of the system clock to all the flip flops shownin FIG. 5 is not shown, which is called the locally generated clock. Forthe four-bit asynchronous binary counter shown in FIG. 5, the systemclock of the circuit is not physically connected to the remaining threeflop flops other than one flip flop used for the least significant bit.

To enable the I/O probing for all four bits output lines of the four bitasynchronous binary counter, one example of expanded targeted circuit towhich the additional IOP-probing circuit is added is shown in FIG. 7a.

In the output probing mode, the configuration of the circuit shown inFIG. 7a is such that the parallel load function of the shift registerarray is made possible by the signal lines to be probed and the dualinput flip flops (PFF0, PFF1, PFF2 and PFF3 in FIG. 7a), along with thetargeted circuit. Simultaneously, it is made possible the parallelloading of the logical values of the targeted signal lines into the dualinput flip flops, by connecting each one input D1 of the dual input flipflops to each of the targeted signal lines y0, y1, y2, y3.

In case of the output probing mode, the outputs of one flip flop presentin the shift register (in this case, indicates the rightmost flip flopPFF3) may be logically connected to the I/O probing line. In the inputprobing mode, the input of one flip flop (in this case, indicates theleftmost flip flop PFF0) present in each of the parallel loadable shiftregister may be logically connected to the input probing line.

Each of the outputs (p0, p1, p2 and p3 of FIG. 7a) of the flip flopsconstituting the parallel loadable shift register array is connected toone input of the dual input flip flop (FF0 in FIG. 7a) replaced amongthe flip flops (FF0, FF1, FF2 and FF3 in FIG. 5) driving the targetedsignal lines (here, indicate y0, y1, y2 and y3), respectively (This maycorrespond to the case where the system clock is connected to the clockinputs of the associated flip flops, and thus here only the FF0 isconsidered).

Alternatively, by being replaced with the dual input flip flops havingthe asynchronous set and the asynchronous reset and controlling theseset and reset inputs, the values held in the flip flops may be thedesired input probing values. Thereafter, a data is input to the dualinput flip flop (here, D2) connected to the output of the related flipflop among the flip flops constituting the shift register array. Thus,with the final synchronous set or synchronous reset, the output of theabove flip flop can be set to either of “0” or “1” (this corresponds tothe case where the system clock is not connected to the clock inputs ofthe related flip flops, and thus here FF1, FF2 and FF3 are considered).

Meanwhile, for this, it is required to further add the FSM for probingthe memory components. The functions of the FSM here is that theasynchronous set or asynchronous reset for the input probing targetedflip flops occurs by the signal values supplied from the shift registerarray, only at a time point as necessary, and that the final synchronousset or synchronous reset for the dual input flip flops occurs by thelogical values of the associated flip flop among the flip flopsconstituting the shift register array.

For this, the combinational circuit's functions as shown in FIG. 7b arenecessary so that the asynchronous set and asynchronous reset of theinput probing targeted flip flops can be controlled using the signallines of the shift register array, the signal lines from the FSM forprobing the memory components, and the operational mode controlling(normal mode*/probing mode) signal lines. If the meanings of the inputsand outputs of the FIG. 7a combinational circuit are differently coded(for example, the meanings of “0” and “1” of the FSMOut are converselyanalyzed), the truth table shown in FIG. 7b is modified.

FIG. 7c shows one example of another expanded targeted circuit to whichthe additional IOP-probing circuit is added to make it possible the I/Oprobing for all four bits output lines of the four bit asynchronousbinary counter.

Difference between both FIGS. 7a and 7 c is that, in case of FIG. 7a,for the flip flops FF1, FF2 and FF3 using the locally generated clock,the dual input flip flops having the asynchronous set/reset are used toperform the input probing with the synchronous set or synchronous resetsubsequent to the asynchronous set or asynchronous reset, while in caseof FIG. 7c, the single input flip flops having the asynchronous set/restand the synchronous enable are used to perform the input probing withthe synchronous disable subsequent to the asynchronous set orasynchronous reset.

For the implementation as shown in FIGS. 7a and 7 c, totally separatenew construction was used for all flip flops used in the shift registerarray providing both the parallel and serial loadings according to themode change, rather than using the flip flops present in the designverification targeted circuit. However, in such a case, the merit isthat the minimal disturbance to the targeted circuit is possible duringthe I/O probing performance, but a drawback of a larger overhead mayappear instead.

The implementation as shown in FIGS. 7e and 7 g can provide the minimaloverhead for the I/O probing by some of the flip flops constituting theshift register array being selected among the flips flops present in thetargeted circuit and modified the selected ones.

In case of the four bit asynchronous binary counter, the smallest scaleof the circuit constitution may comprise only one flip flop directlyconnected to the system clock, but in case of a typically larger scaleof the circuit constitution, since there are mostly the numerous flipflops directly connected to the system clock, the above described schemeis highly preferable in that it greatly reduces the overhead for the I/Oprobing, wherein the scheme uses, as some the flip flops in the shiftregister array, the flip flops partially present in the targetedcircuit.

FIG. 8a illustrates the case where one or more flip flops 78 in thetargeted circuit already have the asynchronous set and the asynchronousreset and the clock inputs of those flip flops are, not directlyconnected to the system clock, but connected to the locally generatedclock or the gated clock.

In this case, as a first method, the flip flops to be input probed arereplaced with the dual input flip flops 77 as described above, such thatthe functional logical behaviors of the original circuit to be verifiedremains unchanged, even if the circuit is modified by adding theadditional IOP-probing circuit including the combinational controlcircuit driving the asynchronous set and asynchronous reset inputs ofthe replaced ones.

FIG. 8b shows such a situation, and the truth table for thecombinational control circuit used is shown in FIG. 8c. The functions ofthe FSM for probing the memory components and synchronized and driven bythe probing clock is to create the asynchronous set/reset enable signal(which is activated in this case), such that, in the input probing mode,the input probing occurs only at specific n-th cycle of the probingclock, by controlling the asynchronous set input and asynchronous resetinput of the dual input flip flops replacing the flip flop to be inputprobed by using the input probing values stored in specific flip flopsin the shift register array constituting the additional IOP-probingcircuit at specific n-th cycle of the probing clock. Also, anotherfunction is to create the asynchronous set/reset enable signal (which isdisabled in this case), such that the asynchronous set and asynchronousreset of the dual input flip flops replacing specific flip flops to beinput probed are disabled at the cycles other than said specific n-thcycle. Meanwhile, in the normal operation mode, the asynchronousset/reset enable signals (which are disabled in this case) are created,which signals allow the expanded targeted circuit to become functionallyequal to the original targeted circuit. Thereby, the control circuitunit is driven which is connected to the asynchronous set input andasynchronous reset input of the dual input flip flop replacing thetargeted flip flops. Also, the control is made such that, with thelogical values of the associated flip flops among the flip flopsconstituting the shift register array, the final synchronous set orsynchronous reset of the dual input flip flop occurs.

As a second method, the flip flops to be input probed are replaced withthe single input flip flops 73 having the synchronous enable, aspreviously described, and the circuit modification is made with theadditional IOP-probing circuit added along with the combinationalcontrol circuit, while the functional logical behaviors of the originaltargeted circuit remain unchanged. Such a situation is shown in FIG. 8e.The truth table of the combinational control circuit used in this caseis shown in FIG. 8f.

The functions of the FSM for probing the memory components andsynchronized and driven by the probing clock is to create theasynchronous set/reset enable signal (which is activated in this case),such that, in the input probing mode, the input probing occurs only atspecific n-th cycle of the probing clock, by controlling theasynchronous set input and asynchronous reset input of the single inputflip flops having the synchronous enable and replacing the flip flop tobe input probed by using the input probing values stored in specificflip flops in the shift register array constituting the additionalIOP-probing circuit at specific n-th cycle of the probing clock. Also,another function is to create the asynchronous set/reset enable signal(which is disabled in this case), such that the asynchronous set andasynchronous reset of the single input flip flops replacing specificflip flops to be input probed are disabled at the cycles other than saidspecific n-th cycle. In the normal operation mode, the function of theFSM is to create the asynchronous set/reset enable signals (which aredisabled in this case) allowing the expanded targeted circuit to becomefunctionally equal to the original targeted circuit. Thereby, thecontrol circuit unit is driven which is connected to the asynchronousset input and asynchronous reset input of the single input flip flopreplacing the targeted flip flops. Also, the control is made such that,with the synchronous enable signal generated from the FSM after theinput probing performance by the asynchronous set or asynchronous reset,the current values of the flip flops related are maintained at thespecific time point.

In case of using RS, JK or T type flip flop other than D type flip flopused in designing the circuit, the D type flip flop and simplecombinational circuit are used together to constitute a circuitfunctionally equal to those structures, and then, the above equivalentcircuit is implemented. In the probing method according to the presentinvention, the method for generating the additional probing circuit canalso be applied to the case of using any kind of flip flops toconstitute a circuit.

In case latch elements are used for the memory components used in thetargeted circuit, prior to the use of the above methods, respectivelatches are modified as shown in FIG. 9 by using the flip flops andcombinational circuit, so that a circuit functionally equivalent to theoriginal latch can be obtained, and then the above methods are applied.

In case there are the memory components which use clock inputs gated bythe result that the I/O probing system control unit investigates thetargeted circuit, an example of another method for implementing thefunction of such an additional IOP-probing circuit is that the systemcontrol unit synthesizes in an automated manner circuits fullysynchronized with respect to the system clock and which are functionallyequivalent to the original targeted circuit and the synthesized circuitsare used as new targeted circuits instead of the original targetedcircuit.

Thereafter, the signal lines of the targeted memory components and dualinput flip flops in one or more RFPDs having the targeted circuitimplemented are used to allow the additional IOP-probing circuit tobecome one or more shift register arrays proving selectively theparallel loading and serial loading functions according to the change inmode. Then, in the output probing mode, after one input of therespective dual input flip flops and the output signal lines of thetargeted memory components are connected together to made it possiblethe parallel loading of the logical values on the output probingtargeted signal lines to each of said dual input memory components, theoutput of one flip flop present in each of one or more shift registerarrays is logically connected to one of the I/O pins functioning as oneor more I/O probing lines of the related RFPD, and then, according tothe probing clock of the shift register and the synchronized shiftingoperation, the logical values of all flip flops of the shift registerare allowed to sequentially appear on the I/O pins serving as the I/Oprobing lines. The input probing mode logically connects to the I/O pinsserving as one or more input probing lines of the related RFPD theinputs of the flip flops present in each of one or more shift registerarrays having the possible parallel and serial loading functionsaccording to the change in mode. Thereby, with the probing clock and thesynchronized shifting operation, the input probing values sequentiallysupplied from the external through the I/O pins serving as the inputprobing line can be loaded to the shift register in a serial manner.Also, since the system clock is directly connected to the clock input ofall memory components to be input probed, the respective outputs of theflip flops constituting one or more shift register arrays whose theparallel loading function is possible can be connected to one input ofthe dual input flip flops driving the respective signal lines to beinput probed.

In case the memories such as RAMs or ROMs are further included in thetargeted circuit and on-chip memory having such memories built in theRFPD is used for the implementation, an additional memory read/writecircuit is further incorporated to the additional IOP-probing circuit.The on-chip memory may be, specifically, a distributed RAM manufacturedby XilinX FPGA, BlockRAM, or Embeded System Block from BlockRAM, AlteraFPGA.

In the output probing mode, the I/O probing system control unit controlsthe additional memory R/W circuit to read all the contents in all orspecific areas in a predetermined order and to send in an automaticmanner them to the I/O probing system control unit through the outputprobing line, a relay module and then a relay cable.

Meanwhile, in the input probing mode, the additional memory R/W circuitwrites the data held in the I/O probing system control unit into all orspecific areas of a writable memory within the targeted circuitimplemented in the RFPD, through the relay cable and relay module andthe input probing line of the RFPD, in an automatic manner andpredetermined order.

One specific example of implementing such an additional memory R/Wcircuit may be attained by the combination of flip flops, multiplexers,and FSM which generates R/W control signal for the memory and addresssequences for all areas of the memory to/from which the read/writeoperations are performed, and further generates clock signals inpreparation for clocked memory employed, as necessary. FIG. 10 showssuch an example in detail. The following is to explain the operation ofsuch a configured additional memory R/W circuit.

In the output probing mode, the FSM 90 for probing the memory has inputlines for receiving the operational mode controlling (normalmode*/probing mode), the probing mode controlling (input probing”/outputprobing) signal line and the memory R/W (absent”/present) signal linefor the probing.

Also, the FSM 90 clocked by the probing clock generates a R/W controlsignal 81 for the memory, address signal 82 for specific address, aselective input signal 84 for multiplexer 1 83 in a memory input stage,and memory clock signal 85, and has output lines which output the R/Wcontrol signal 81 and the address signal 82.

If it is needed, the memory clock signal 85 is also permitted to appearon an output part of the multiplexer 1 83 so that the current contentsheld in specific address can be thereby present on an output part 85 ofthe memory. Then, an enable signal for the flip flops 87 in a memoryoutput stage is generated to store the values of the memory output stage86 in the flip flops 87. Thereafter, an input selective signal for theflip flops 87 is generated, thereby the flip flops 87 being used as ashift register synchronized with the probing clock which performs theshifting operation through which the current contents in specificaddresses sequentially appears on the output probing line. Thus, theread-in of the current contents held in specific addresses is possible.The FSM 90 automatically, orderly performs the read-in operation for alladdresses of the memory.

In the input probing mode, the FSM 90 receives the operational modecontrolling (normal mode*/probing mode) signal line, the probing modecontrolling (input probing*/output probing) signal line, the memory R/W(absent*/present) for the probing, and the probing clock, and inrespense thereto, provides, on the output part of the multiplexer 1 83in the memory input stage, the memory R/W control signal 81, the addresssignal 82 for specific address, and the selective input signal 84 forthe multiplexer 1 83 in the memory input stage. Thus, the specificaddress of the memory to which the write is to be performed can beaccessed. Then, in response to the probing clock input, the shiftregister 88 in the memory input stage performs the shifting operationthereof, whereby the data to be written to the specific addresses of thememory are sequentially input through the input probing line. At a timepoint at which the shifting operation is completed, the data are storedin the shift register 88 in the data input stage, the selective signalfor the selective signal lines of the multiplexer 2 89 in the data inputstage is generated, and, if necessary, the memory clock signal 85 isgenerated, so that the data stored in the shift register 88 can bewritten to the specific addresses of the memory. The FSM 90 is operatedto write the date into the specific addresses of the memory, asdescribed above.

To read/write the memory, the FSM 90 internally may have an addressgenerator for address areas of the R/W memory, and the above mentionedadditional memory R/W circuit can also be applied to two-port memory,similarly.

Again, in order to perform the I/O probing operation in case ofincluding the memory in the design verification targeted circuit, theI/O probing system control unit further has the additional IOP-probingcircuit added to the targeted circuit to generate a target circuitexpanded to one or more RFPDs, such that the additional IOP-probingcircuit can perform the read/write operation from/to the memory, as wellas the I/O probing operation for the targeted circuit.

In the present invention, the output probing line and the input probingline may exist as an separate uni-directional probing line, or as abi-directional probing line that the output probing line and the inputprobing line are combined.

As a probing clock for use in the present invention, an extra clock, notthe system clocks used for the design verification target circuit, maybe used, or one of the system clocks may be used.

By adopting the above described input/output probing apparatus andmethod, an emulation/simulation mixed design verification can beperformed by using an arbitrary prototyping board, on which at least onesemiconductor chip is mounted in which an extended design verificationtarget circuit formed by adding the IOP-probing supplemental circuit tothe design verification target circuit is implemented, and an arbitrarysimulator.

That is, the mixed emulation/simulation method for design verificationincludes a step in which the input/output probing system controllerreceives the memory and the probing target signal lines existing in thedesign verification target circuit or memory block and probing targetsignals existing in the design verification HDL code.

At this time, in order to implement a design verification target circuitin at least one RFPD mounted on the prototyping board, the outputprobing target signals lines or logic values in a specific time zone inthe reading target memory region or at the time point when a particularsituation occurs appear sequentially in the output probing line only fora predetermined time.

And, the mixed emulation/simulation method for design verification alsoincludes a step in which an extended design verification target circuitis generated by adding the IOP-probing supplementary circuit to thedesign verification target circuit allocated in at least one RFPDmounted on the prototyping board, so that the input probing targetsignal lines or the writing target memory area can have logic valuesapplied to the input probing line at a specific time zone.

For the output probing target signal lines and the reading target memoryarea, the logic values and the memory content at a specific time zone onthe output probing target signal lines appear on the output probing lineof the corresponding RFPD by using the IOP-probing supplementarycircuit.

The value appearing on the output probing line is transmitted throughthe input/output probing interface module to the server computer, sothat the simulator may have the current state information of the designverification target circuit as an initial state value for simulator.

Meanwhile, for the input probing target signal lines and the writingtarget memory area, input probing data is generated from the stateinformation obtained through simulation in the server computer.Thereafter, the data is applied to the input probing target signal linesthrough a interface module and a interface cable while beingsynchronized only with the probing clock, or is applied thereto whilechanging suitably the probing mode to an input probing mode or to anoutput probing mode through a probing mode control signal line, so thatthe logic values transmitted through the input probing line are inputtedto the logic value of the input probing target signal lines and to thememory area, so that the state information of the design verificationtarget circuit implemented in the RFPD is identical to the stateinformation generated through simulation for a predetermined time in thesimulator.

For the mixed emulation/simulation in an automated manner by using theinput/output probing apparatus and the input/output probing method,execution switching should be automatically made between emulation andsimulation. This is called as execution mode switching, which is madewhen a specific condition is met (for example, at the time when aspecific value is written in a specific register of a circuit twice).The condition is called an execution mode switching condition. There areat least two execution mode switching conditions in the overallverification process on a time basis, that is, a condition before areference time and a condition after the reference time. In this case,in an arrangement from a first set condition to the later set condition,at a time point when a condition is met, the execution mode switchingoccurs from emulation to simulation or from simulation to a logicemulation.

For this purpose, the execution mode switching conditions need to bestored in a queue, which is called an execution mode switching conditionqueue. It is maintained in a data structure in the input/output probingsystem controller.

The extended design verification target circuit, which is generated byadding the IOP-probing supplementary circuit to the design verificationtarget circuit, is implemented in at least one RFPD on the prototypingboard.

In the course of performing a verification on the emulation basis byexecuting the prototyping board, in case where a switchover tosimulation is needed at a specific time point or at a time point when aspecific situation occurs, the input/output probing system controllerdetects it and stops performing of emulation.

After at least one RFPD is switched from a normal mode to an outputprobing mode under the control of the input/output probing systemcontroller, when the probing clock is applied to the RFPD, the logicvalues of the signal lines, subjected to the probing through at leastone output probing line connected to the output of a single flipflopexisting in at least one shift register array structure, is transmittedto the server computer via the input/output probing interface module.

The input/output probing time point may be statically determined beforeperforming emulation, or may be dynamically determined such as a timepoint when a specific situation occurs during performing of emulation.

In order to determine an input/output probing time point dependent onthe emulation situation such as the time point when the specificsituation occurs, an external equipment such as a logic analyzer is usedto observe it and determine an input/output probing time point. Or, aninput/output probing time point detector circuit for detecting anoperation situation is added in the RFPD so as to output an input/outputprobing situation, which can be detected by the input/output probingsystem controller to start input/output probing.

In case that the input/output probing time point detector circuit isadded together with the IOP-probing supplementary circuit to the designverification target circuit in the RFPD, its natural generation andaddition is also handled by the input/output probing system controller.

The input/output probing apparatus and input/output probing methodincludes a step of receiving a memory and probing target signal linesexisting in the design verification target circuit or a memory block andprobing target signals existing in the design verification HDL code bythe input/output probing system controller.

Also, the input/output probing apparatus and input/output probing methodfurther includes a step in which, in order to implement a designverification target circuit in at least one RFPD mounted on theprototyping board, the output probing target signal lines or the logicvalues at a specific time zone in or at a time point when a specificsituation occurs in the reading target memory area sequentially appearin the output probing line for a predetermined time, and in order forthe input probing target signal lines or the writing target memoryregion to have logic values applied in a specific time zone in the inputprobing line, the IOP-probing supplementary circuit is added to thedesign verification target circuit allocated in at least one RFPDmounted on the prototyping board, thereby generating an extended designverification target circuit.

Also, the input/output probing apparatus and input/output probing methodfurther includes a step in which, for the output probing target signallines and the reading target memory area, the logic values and thememory content at a specific time zone on the output probing targetsignal lines appear in the output probing line of the corresponding RFPDby using the IOP-probing supplementary circuit, and the value appearingin the output probing line is transmitted through the input/outputprobing interface module to the server computer, and meanwhile, for theinput probing target signal lines and the writing target memory area,after an input probing data is generated from the state informationobtained by the server computer, the input probing data is synchronizedonly with the probing clock and applied to the input probing targetsignal lines of the corresponding RFPD through the input/output probinginterface module, the input probing data is synchronized with theprobing clock an applied to the input probing target signal lines of thecorresponding RFPD through the input/output probing interface modulewhile adequately changing the probing mode between the input probingmode and the output probing mode, so that the logic value of the inputprobing target signal lines and the content of the writing target memoryregion are replaced with the logic values transmitted through the inputprobing line, and thus, the state information of the design verificationtarget circuit implemented in the RFPD is identical to the stateinformation obtained by the server computer.

The mixed emulation/simulation method according to the input/outputprobing apparatus and the input/output probing method of the presentinvention includes: a step in which a design verification target circuitand a name of ASIC vendor library name are inputted to the servercomputer; a step in which probing target signal lines on the designverification target circuit required for mixed verification and a memoryarea are assigned additionally as required; a step in which the outputprobing target signal lines and the logic value at a specific time zoneof the memory area appears for a predetermined time, and an extendeddesign verification target circuit is generated by adding an IOP-probingsupplementary circuit to the design verification target circuitimplemented in at least one RFPD so that the input probing target signallines and the memory area may have the logic values applied to the inputprobing line at a specific time zone; a step in which the extendeddesign verification target circuit is implemented in at least one RFPD,and while the implemented design verification target circuit is beingoperated, output probing is performed for at least one RFPD under thecontrol of the input/output probing system controller at an arbitrarytime point set by a user or at a time point when a situation occurs, sothat the content of the memory area and the logic values at the specifictime zone of the output probing target memory devices can appear in theoutput probing line of at least one RFPD by using the IOP-probingsupplementary circuit; a step in which the value of the thusly appearedvalue of the output probing line is transmitted through the input/outputprobing interface module to the server computer and automatically set asa simulation initial state value for performing simulation by asimulator; and a step in which the state information of the designverification targer circuit obtained through simulation at a time pointset by the user or in a situation during simulation by simulator, isowned by the memory device and the memory area subjected to the inputprobing through the input probing line of the RFPD mounted on theprototyping board passing through the input/output probing interfacefrom the server computer by employing the input probing method using theIOP-probing supplementary circuit, thereby automatically performingemulation following simulation.

The mixed emulation/simulation method according to the input/outputprobing apparatus and the input/output probing method includes a step inwhich a design verification target HDL code and an ASIC vendor libraryname are inputted to the server computer; a step in which probing targetsignals on the design verification target HDL code required for mixedverification and a memory area are assigned additionally as required; astep in which an extended design verification HDL code is generated byadding an IOP-probing supplemental HDL code to the design verificationtarget HDL code implemented in at least one RFPD, so that output probingtarget signals and a logic value at a specific time zone fo the memoryarea appear in the output probing line only for a predetermined time andthe input probing target signals and the memory area owns a logic valueapplied to the input probing line at a specific time zone; a step inwhich after the extended design verification target HDL code isimplemented in the RFPD, while a circuit functionally equivalent to theimplemented design verification target HDL code is being operated,output probing is performed for the RFPD at a time point set by the useror at a time point at which a situation occurs, so that logic values andthe content of the memory area at the specific time zone of the outputprobing target memory devices appear in the output probing line of theRFPD by using the IOP-probing supplementary circuit; a step in which thevalue of the thusly appearing output proving line is transmitted throughthe input/output probing interface module to the server computer andautomatically set as a simulation initial state value for performingsimulation by means of a simulator; and a step in which the stateinformation of the design verification target HDL code obtained throughsimulation at a time point set by the user or in a situation duringsimulation by simulator, is owned by the memory device and the memoryarea subjected to the input probing through the input probing line ofthe RFPD mounted on the prototyping board passing through theinput/output probing interface from the server computer by employing theinput probing method using the IOP-probing supplementary circuit,thereby automatically performing emulation following simulation.

FIG. 11 is a flow chart of the input/output probing method in accordancewith one embodiment of the present invention, which is performed by theserver computer 20 of FIG. 1.

According to the input/output probing method, first an ASIC vendorlibrary name and a design verification target circuit are inputted, or atarget verification target HDL code is inputted (S50). An input/outputprobing target signal line is inputted (S52). After an IOP-probingsupplementary circuit is generated by semiconductor chips of aprototyping board and added to a design verification target circuit,thereby generating an extended design verification target circuit, orafter an IOP-probing supplementary HDL code is generated, it is added toa design verification target HDL code, thereby generating an extendeddesign verification target HDL code (S54).The extended designverification target circuit or the extended design verification targetHDL code is implemented in a corresponding semiconductor chip on theprototyping board (S56). In a normal mode, a circuit verificationprocess is performed (S70). It is checked whether probing is to beperformed (S72), and if probing is to be performed, it proceeds to thestep S74, or otherwise, it proceeds to the step S82. In the step S74, itis checked whether it is output probing (S74), and if it is outputprobing, it proceeds to the step S80, or if it is input probing, itproceeds to the step S76. In the step of S74, a server computergenerates an input probing data and proceeds to the step S78 (S76). Inthe step S78, after it is switched to an input probing mode, the servercomputer applies the input probing data to the input probing linethrough an input/output probing interface module to perform inputprobing and proceeds to the step S82 (S78). In the step S80, after it isswitched to an output probing mode, the value appearing in the outputprobing line is transmitted through the input/output probing interfacemodule to the server computer, thereby completing output probing, andproceeds to the step of S82 (S80). In the step S82, it is checkedwhether the design verification has been completed, and if it has beencompleted, the over process is ended, or otherwise, it proceeds to thestep S70 (S82).

In this manner, the input/output probing apparatus and the input/outputprobing method of the present invention are employed, so that the designverification can be freely performed in turn without any restriction tothe number of times of switching between emulation and simulation forthe design verification target circuit.

FIG. 12 is a schematic view showing a construction of a mixedverification environment using emulation and simulation as a stand-alongmode. Though FIG. 12 has the same elements as those of the input/outputprobing apparatus of FIG. 1, the apparatus of FIG. 12 is different fromthat of FIG. 1 in the aspect that it further includes a simulator 34 toperform emulation and simulation mixedly.

The prototyping board perform emulation and the simulator for performingsimulation are preferably performed in a distributed environment throughnetwork. Accordingly, FIG. 13 is a schematic view showing a constructionof the mixed verification environment using emulation and simulationthrough a local and remote area network (36).

FIG. 14 is a schematic view showing an environment to perform emulationby employing the input/output probing apparatus consisting of theinput/output probing interface module 26 and the input/output systemcontroller 32, the prototyping board 44 and the server computer 20, andsimulation by using the simulation server computer 34 and the simulator35 in a distributed environment on the inter-network 37 (i.e., theInternet, etc) having a gateway 38.

FIG. 15 is a flow chart of the mixed emulation/simulation method bysteps in accordance with one embodiment of the present invention, whichis performed by the server computer 20 illustrated in FIGS. 12, 13 and14.

In the step S100, after a design verification target circuit and an ASICvendor library name used when designed are inputted by using the servercomputer, based on which an extended design verification target circuitis generated by adding an IOP-probing supplementary circuit to at leastone RFPD of a prototyping board that can be subjected to input/outputprobing by using the input/output probing system controller in anautomated manner, and the extended design verification target circuit isimplemented in the RFPD on the prototyping board, and then servercomputer prepares to perform simulation of the design verificationtarget circuit by using a simulator (S100).

In the step S102, an initial state information (values for every memorydevice (such as flipflops and latches) in a circuit) for the designverification target circuit subjected to the mixed verification ofemulation and simulation are inputted by using the server computer 20 sothat the current state information of a simulation circuit for asimulator and of an emulation circuit for a prototyping board can be thesame as the initial state information, verification method switchingtime pint or switching condition sequence is determined and stored in anexecution mode switching condition queue, of which the forefront of thequeue becomes the current verification method switching time point andswitching condition (S102).

In the step S104, it is determined whether simulation is to be performedor whether emulation is to be performed with the current stateinformation (S104).

In case that emulation is performed, it proceeds to the step S106 andperforms emulation by using the prototyping board until the currentverification stoppage time point or stoppage condition is met (S106).

In the step S108, it is checked whether an additional verificationprocess is required, and if it is not required, the overall process isended, while, if it is required, it proceeds to the step S109 (S108).

In the step S109, it is checked whether the execution mode switchingcondition queue is empty, and if it is not empty, it proceeds to thestep S115, while, if it is empty, it proceeds to the step S111 (S109).

In the step S111, it is checked whether a new verification methodswitching time point or switching condition sequence is to be stored inthe execution mode switching condition queue, and if it does not need tobe stored, it proceeds to the step S108, while, if it needs to bestored, it proceeds to the step S113 (S111).

In the step S113, the new verification method switching time point orswitching condition sequence is stored in the execution mode switchingcondition queue and it proceeds to the step S115 (S113).

In the step S115, the current verification method switching time pointand switching condition are newly set with the execution mode switchingcondition queue and proceeds to the step S117 (S115).

In the step S117, it is checked whether the current verification methodis emulation or simulation, and if it is emulation, it proceeds to thestep S134, while, if it is simulation, it proceeds to the step S132(S117).

In the step S132, input probing is performed for the RFPDs so that theextended design verification target circuit implemented in the RFPD onthe prototyping board has the same state information as the currentstate information of the design verification target circuit at thecurrent verification stoppage time point obtained through simulation onthe server computer, and proceeds to the step S106 (S132).

In the step S134, output probing is performed for at least one RFPD onthe prototyping board so that the design verification target circuitbeing performed by the simulator on the server computer can have thesame state information as the current state information of the designverification target circuit at the current verification stoppage timepoint obtained by output probing for the extended design verificationtarget circuit implemented in the RFPD on the prototyping board andproceeds to the step S120 (S134).

In the step S120, simulation is performed by using the simulator untilthe current verification method switching time point or switchingcondition is met, and proceeds to the step S108 (S120).

FIG. 16 is a flow chart of the mixed simulation/emulation method bysteps in accordance with another embodiment of the present invention,which is performed by the server computer 20 as illustrated in FIGS. 12,13 and 14.

In the step S300, after a design verification target HDL code and anASIC vendor library name used when designed are inputted by using theserver computer, based on which an extended design verification targetHDL code is generated by adding an IOP-probing supplementary HDL code toat least one RFPD of a prototyping board that can be subjected toinput/output probing by using the input/output probing system controllerin an automated manner, and the extended design verification target HDLcode is implemented in the RFPD on the prototyping board, and thenserver computer prepares to perform simulation of the designverification target HDL code by using a simulator (S300).

In the step S302, an initial state information (values for every memorydevice (such as flipflops and latches) in a circuit) for the designverification target HDL code subjected to the mixed verification ofemulation and simulation are inputted by using the server computer 20 sothat the current state information of a simulation circuit for asimulator and of an emulation circuit for a prototyping board can be thesame as the initial state information, verification method switchingtime pint or switching condition sequence is determined and stored in anexecution mode switching condition queue, of which the forefront of thequeue becomes the current verification method switching time point andswitching condition (S302).

In the step S304, it is determined whether simulation is to be performedor whether emulation is to be performed with the current stateinformation (S304).

In case that emulation is performed, it proceeds to the step S306 andperforms emulation by using the prototyping board until the currentverification stoppage time point or stoppage condition is met (S306).

In the step S308, it is checked whether an additional verificationprocess is required, and if it is not required, the overall process isended, while, if it is required, it proceeds to the step S309 (S308).

In the step S309, it is checked whether the execution mode switchingcondition queue is empty, and if it is not empty, it proceeds to thestep S315, while, if it is empty, it proceeds to the step S311 (S309).

In the step S311, it is checked whether a new verification methodswitching time point or switching condition sequence is to be stored inthe execution mode switching condition queue, and if it does not need tobe stored, it proceeds to the step S308, while, if it needs to bestored, it proceeds to the step S313 (S311).

In the step S313, the new verification method switching time point orswitching condition sequence is stored in the execution mode switchingcondition queue and it proceeds to the step S315 (S313).

In the step S315, the current verification method switching time pointand switching condition are newly set with the execution mode switchingcondition queue and proceeds to the step S317 (S315).

In the step S317, it is checked whether the current verification methodis emulation or simulation, and if it is emulation, it proceeds to thestep S334, while, if it is simulation, it proceeds to the step S332(S317).

In the step S332, input probing is performed for the RFPDs so that theextended design verification target HDL code implemented in the RFPD onthe prototyping board has the same state information as the currentstate information of the design verification target HDL code at thecurrent verification stoppage time point obtained through simulation onthe server computer, and proceeds to the step S306 (S332).

In the step S334, output probing is performed for at least one RFPD onthe prototyping board so that the design verification target HDL codebeing performed by the simulator on the server computer can have thesame state information as the current state information of the designverification target HDL code at the current verification stoppage timepoint obtained by output probing for the extended design verificationtarget HDL code implemented in the RFPD on the prototyping board andproceeds to the step S320 (S334).

In the step S320, simulation is performed by using the simulator untilthe current verification method switching time point or switchingcondition is met, and proceeds to the step S308 (S320).

As so far described, according to the input/output probing apparatus andthe input/output probing method using the same of the present invention,the design verification target circuit emulated after being implementedin the semiconductor chips mounted on the prototyping board can berapidly and effectively debugged. Also, since the state information isautomatically exchanged with the design verification target circuitsimulated by the simulator, so that a high speed functional verificationand an accurate timing verification can be performed in turn, therebyperforming a very effective verification.

As the present invention may be embodied in several forms withoutdeparting from the spirit or essential characteristics thereof, itshould also be understood that the above-described embodiments are notlimited by any of the details of the foregoing description, unlessotherwise specified, but rather should be construed broadly within itsspirit and scope as defined in the appended claims, and therefore allchanges and modifications that fall within the meets and bounds of theclaims, or equivalence of such meets and bounds are therefore intendedto be embraced by the appended claims.

What is claimed is:
 1. An input/output probing apparatus comprising: aninput/output probing system controller; and an input/output probinginterface module wherein the input/output probing system controllergenerates IOP-probing supplementary circuit for a design verificationtarget circuit implemented in at least one semiconductor chip mounted ona prototyping board or an HDL code for indicating behavior of theIOP-probing supplementary circuit adds the IOP-probing supplementarycircuit or the HDL code indicating the behavior of the IOP-probingsupplementary circuit to the design verification target circuit or tothe HDL code, so as to implement an input/output probing-feasible designverification target circuit in at least one semiconductor chip, therebyperforming an input/output probing by using the IOP-probingsupplementary circuit or the HDL code indicating the behavior of theIOP-probing supplementary circuit.
 2. The apparatus according to claim1, wherein the IOP-probing supplementary circuit or the HDL codeindicating the behavior of the IOP-probing supplementary circuit isautomatically generated by operating the input/output probing systemcontroller.
 3. The apparatus according to claim 2, wherein before theIOP-probing supplementary circuit or the HDL code indicating thebehavior of the IOP-probing supplementary circuit is automaticallygenerated by operating the input/output probing system controller, theinput/output probing system controller checks the design verificationtarget circuit or the design verification target HDL code andautomatically generates a converted and new design verification targetcircuit or a new design verification target HDL code which isfunctionally equivalent to the original circuit or to the original HDLcode and completely synchronized with a single clock, and performsinput/output probing based on it.
 4. The apparatus according to claim 2,wherein the input/output system controller additionally generates asituation detecting unit for detecting a switching condition to aprobing mode for input/output probing and implements the situationdetecting unit in the semiconductor chip.
 5. The apparatus according toclaim 2, wherein, in the output probing mode, the supplementary circuitof the extended design verification target circuit obtained by addingthe IOP-probing supplementary circuit to the design verification targetcircuit has a shift register structure in which a parallel load isavailable for an output probing target memory device, of which the shiftregister has the logic values of the memory devices subjected to outputprobing by parallel loading just before shifting operation synchronizedwith a probing clock, to thereby perform reading for the output probingtarget memory, and in the input probing mode, the supplementary circuitpart has a shift register structure in which a serial load is availablefor an input probing target memory device, and by using the shiftingoperation, a synchronous setting operation or a synchronous resettingoperation, a synchronous setting operation or a synchronous resettingoperation followed by an asynchronous setting operation or anasynchronous resetting operation and a synchronous disabling operationfollowed by an asynchronous setting operation or an asynchronousresetting operation are selectively adopted to each memory devicesubjected to input probing, to input an input probing value to thememory devices subjected to the input probing and perform a recording inthe input probing target memory as required, and in a normal mode, eventhough the IOP-probing supplementary circuit is added to the designverification target circuit, the functional logic property of the designverification target circuit is not changed.
 6. The apparatus accordingto claim 5, wherein, in an output probing mode, the extended designverification target circuit including the IOP-probing supplementarycircuit, along with the design verification target circuit allocated inthe RFPD, has at least one shift register array structure in which aparallel load is available for the output probing target memory devicesin the probing target RFPD by probing target signal lines and dual-inputflipflops, connects each input of the dual-input flipflop to eachprobing target signal line to enable each of the probing target signallines to be parallely loaded in the dual-input flipflop, logicallyconnects the output of a single flipflop existing in each of at leastone shift register array structure to at least one output probing lineof the RFPD, for an additional output probing target memory asnecessary, a memory probing finite state machine included in acorresponding RPFD renders the output of a single flipflop existing ineach shift register array structure which stores the content of acorresponding area read by reading operation to appear in at least oneoutput probing line of the RFPD by shifting operation, and in an inputprobing mode, for the input probing target memory devices, an input of asingle flipflop existing in at least one shift register array structurein which parallel load is available is logically connected to at leastone input probing line of the RFPD, so as to be able to serially loadthe input probing value to the shift register according to the shiftingoperation synchronized with the probing clock, so that, in case that asystem clock is connected to the clock input of each memory device inwhich each output of the flipflops constructing at least one parallelyloadable shift register array drives each input probing target signalline, each memory device is connected to one input of each replaceddual-input memory device, or a combining circuit is added to a memorydevice data input terminal so that each memory device is synchronouslyset or reset with the output vale of each flipflop constructing at leastone parallely loadable shift register array, meanwhile, for the memorydevices each driving the input probing target signal lines, in case thatthe system clock is not physically connected with the clock input of acorresponding memory device, the corresponding memory device isconstructed as a memory device having an asynchronous set input and anasynchronous reset input and a combining circuit is added to control theasynchronous set input and the asynchronous reset input of the memorydevice, so that the logic value of the memory device is reset as adesired input probing value through a process including an asynchronoussetting operation or an asynchronous reset operation for the memorydevice, and for an additional input probing target memory as necessary,a logic value is applied from at least one input probing line of theRFPD to each input of the flipflop at the very first portion existing ineach shift register array structure in the memory data input terminal byshifting operation, so that, after the shift register in the memory datainput terminal completely performs shifting operation, the finite statemachine for memory probing included in a corresponding RFPD contains thecontent to be written in a specific address by writing operation in acorresponding area, by which the memory probing finite state machinesuccessively writes for a specific address in the memory, therebyperforming input probing for a memory.
 7. The apparatus according toclaim 6, wherein the output probing line and the input probing lineexist separately as an independent unidirectional probing line.
 8. Theapparatus according to claim 6, wherein the output probing line and theinput probing line exist as mutually combined bi-directional probingline.
 9. The apparatus according to claim 5, wherein the shift registerarray of the IOP-probing supplementary circuit is constructed byserially connecting dual-input flipflops, or is constructed the HDL codecorresponding to the behavior of the shift register array of the HDLcode indicating the behavior of the IOP-probing supplementary circuit asan HDL code indicating behavior of the serially connected dual-inputflipflops.
 10. The apparatus according to claim 5, wherein, in theprobing mode, the physically same probing clock is applied to everyclock input of the dual-input flipflops of the shift register array ofthe IOP-probing supplementary circuit, and the probing clock and thesystem clock are controlled by the input/output probing interface moduleand the input/output probing system controller.
 11. The apparatusaccording to claim 2, wherein in case that the design verificationtarget is expressed as the HDL code, in the output probing mode, theadded HDL code part of the extended design verification target HDL codecompleted by adding the supplementary HDL code indicating behavior ofthe IOP-probing supplementary circuit to the design verification targetHDL code indicates behavior of a shift register that a parallel load isavailable for an output probing target memory device, of which signalvalues of the signal lines of the register HDL code are replaced withsignal values subjected to an output probing by a parallel load in theHDL code indicating the behavior of the shift register just beforeshifting operation synchronized with the probing clock, thereby readinga specific area of the output probing target memory, and in an inputprobing mode, the supplementary HDL code part has a shift registerstructure in which a serial load is available for an input probingtarget memory device, and performs a shifting operation synchronizedwith the probing clock, and a synchronous setting operation or asynchronous resetting operation, a synchronous setting operation or asynchronous resetting operation followed by an asynchronous settingoperation or an asynchronous resetting operation and a synchronousdisabling operation followed by an asynchronous setting operation or anasynchronous resetting operation is performed for signals of the HDLcode indicating the behavior of the memory devices of the HDL codesubjected to input probing by using the shifting operation, so that thelogic values of the signals subjected to the input probing become theinput probing values, to record in the input probing target memory asnecessary, and in a normal mode, even though an IOP-probingsupplementary circuit is added, a supplementary HDL code is constructedin a manner that it does not change the behavior of the designverification HDL code.
 12. An input/output probing method in which aserially loadable shift register array for input probing for at leastone flip-flop in which a system clock is not directly applied to a clockinput of at least one flip-flop existing in the design verificationtarget circuit and a locally generated clock or gated clock is inputtedthereto, and an input probing supplementary circuit having a finitestate machine and a controller for generating and outputting anasynchronous set/reset activation signal at a specific time point areadded to a design verification target circuit, subjected to inputprobing, to thereby generate an extended design verification targetcircuit, and in an input probing mode, after input probing values aresequentially loaded from an external source to the shift register arraystructure through a serial loading synchronized with the probing clock,signal values controlling the asynchronous set and the asynchronousreset of the flip-flop are generated by said controller on the basis ofan input probing value for the flip-flop subjected to a correspondinginput probing among the input probing values loaded to each flip-flop ofthe shift register array, an asynchronous set/reset activation outputvalue for the flip-flop subjected to the input probing, the output valuebeing generated from the finite state machine, and an operation modecontrol value applied from an external source, from which, in the inputprobing mode, input probing is performed through a process including anoperation of controlling the asynchronous set input and the asynchronousreset input of the flip-flop subjected to the input probing, meanwhile,in a normal operation mode, the extended design verification targetcircuit generated by adding the input probing supplementary circuit tothe original design verification target circuit is able to perform thefunctionally equivalent operation with the original design verificationtarget circuit.
 13. A mixed emulation/simulation method in which aninput/output probing is performed for at least one semiconductor chip byemulation for verifying by using at least one semiconductor chip whichimplements an extended design verification target circuit obtained byadding an IOP-probing supplementary circuit to the design verificationtarget circuit which includes using an input/output probing interfacemodule wherein an input/output probing system controller generatesIOP-probing supplementary circuit for a design verification targetcircuit implemented in at least one semiconductor chip mounted on aprototyping board or an HDL code for indicating behavior of theIOP-probing supplementary circuit adds the IOP-probing supplementarycircuit or the HDL code indicating the behavior of the IOP-probinqsupplementary circuit to the design verification target circuit or tothe HDL code, and by simulation for verifying the design verificationtarget circuit by using a simulator, and emulation and simulation areperformed in turn more than one time as necessary by exchanging stateinformation in an automated manner between an arbitrary prototypingboard and an arbitrary simulator.
 14. The method according to claim 13,wherein the state information is wholly exchanged in an automated mannerbetween an arbitrary prototyping board and an arbitrary simulator by theIOP-probing supplementary circuit-based input/output probing.
 15. Themethod according to claim 13, wherein the state information is partiallyexchanged in an automated manner between an arbitrary prototyping boardand an arbitrary simulator by the IOP-probing supplementarycircuit-based input/output probing.
 16. The apparatus according to claim1, wherein the semiconductor chip at least one of a FPGA, a CPLD or anASIC chip.
 17. The method according to claim 13, wherein a simulationaccelerator is used instead of the simulator.
 18. The method accordingto claim 13, wherein a logic emulator or a system emulator is usedinstead of the prototyping board.
 19. A mixed emulation/simulationmethod comprising the steps of: inputting a design verification targetcircuit and an ASIC vendor library name used in designing by using aserver computer, generating an extended design verification targetcircuit including an IOP-probing supplementary circuit available forinput/output probing by using an input/output probing system controllerin an automated manner to thereby implement the extended designverification target circuit on a prototyping board, and preparingsimulation for the design verification target circuit by using anarbitrary simulator in the server computer; inputting initial stateinformation on the design verification target circuit subjected to themixed verification by using the server computer so as to make thecurrent state information on a simulation circuit for an arbitrarysimulator and on an emulation circuit in an arbitrary prototyping boardto be the same as the initial state information; determining which ofsimulation and emulation is to be performed first; determining anoperating mode switching conditions between simulation and emulationduring the process, storing the conditions in he operating modeswitching condition queue on a time order, and using the forefront ofthe queue as a switching time point and a switching condition; selectingeither emulation or simulation suitable to the current operating modeand proceeding design verification; and discontinuing performing of thecurrent design verification method at a time when a switching time pointor a switching condition is met with the current verification method,newly setting a switching time point and switching condition of thecurrent verification method in the operating mode switching queue,switching the current operating mode to a different operating mode, andsuccessively performing a design verification of a design verificationmethod different to the verification method that has been performed byfar, through exchanging state information, subsequent to the formerverification method, by employing the input/output probing method usingthe IOP-probing supplementary circuit and the input/output probingapparatus implemented in at least one semiconductor chip mounted on thearbitrary prototyping board which performs emulation, wherein emulationand simulation are performed in turn until the operating mode switchingqueue becomes empty.
 20. A mixed emulation/simulation method comprisingthe steps of: inputting a design verification target circuit and an ASICvendor library name used in designing by using a server computer,generating an extended design verification target circuit including anIOP-probing supplementary circuit available for input/output probing byusing an input/output probing system controller in an automated mannerto thereby implement the extended design verification target circuit inat least one semiconductor chip mounted on a prototyping board, andpreparing simulation for the design verification target circuit by usingan arbitrary simulator in the server computer; inputting initial stateinformation on the design verification target circuit subjected to themixed verification by using the server computer so as to make thecurrent state information on a simulation circuit for an arbitrarysimulator and on an emulation circuit in an arbitrary prototyping boardto be the same as the initial state information; determining which ofsimulation and emulation is to be performed first; determining anoperating mode switching conditions between simulation and emulationduring the process, storing the conditions in he operating modeswitching condition queue on a time order, and using the forefront ofthe queue as a switching time point and a switching condition; selectingeither emulation or simulation suitable to the current operating modeand proceeding design verification; and discontinuing performing of thecurrent design verification method at a time when a switching time pointor a switching condition is met with the current verification method,newly setting a switching time point and switching condition of thecurrent verification method in the operating mode switching queue,switching the current operating mode to a different operating mode, andsuccessively performing a design verification of a design verificationmethod different to the verification method that has been performed byfar, through exchanging state information, subsequent to the formerverification method, by employing the input/output probing method usingthe IOP-probing supplementary circuit and the input/output probingapparatus implemented in at least one semiconductor chip mounted on thearbitrary prototyping board which performs emulation, wherein emulationand simulation are performed in turn until the operating mode switchingqueue becomes empty.
 21. A mixed emulation/simulation method comprisingthe steps of: inputting a design verification target HDL code by using aserver computer, generating an extended design verification target HDLcode including an IOP-probing supplementary HDL code available forinput/output probing by using an input/output probing system controllerin an automated manner to thereby implement the extended designverification target HDL code in at least one semiconductor chip mountedon a prototyping board, and preparing simulation for the designverification target HDL code by using an arbitrary simulator in theserver computer; inputting initial state information on the designverification target HDL code subjected to the mixed verification byusing the server computer so as to make the current state information ona simulating HDL code for an arbitrary simulator and on an emulating HDLcode in an arbitrary prototyping board to be the same as the initialstate information; determining which of simulation and emulation is tobe performed first; determining an operating mode switching conditionsbetween simulation and emulation during the process, storing theconditions in he operating mode switching condition queue on a timeorder, and using the forefront of the queue as a switching time pointand a switching condition; selecting either emulation or simulationsuitable to the current operating mode and proceeding designverification; and discontinuing performing of the current designverification method at a time when a switching time point or a switchingcondition is met with the current verification method, newly setting aswitching time point and switching condition of the current verificationmethod in the operating mode switching queue, switching the currentoperating mode to a different operating mode, and successivelyperforming a design verification of a design verification methoddifferent to the verification method that has been performed by far,through exchanging state information, subsequent to the formerverification method, by employing the input/output probing method usingthe IOP-probing supplementary HDL code and the input/output probingapparatus implemented in at least one semiconductor chip mounted on thearbitrary prototyping board which performs emulation, wherein emulationand simulation are performed in turn until the operating mode switchingqueue becomes empty.
 22. An input/output probing method comprising thesteps of: inputting an ASIC vendor library name and design verificationtarget circuit or a design verification target HDL code; inputting aninput/output probing target signal line; generating an IOP-probingsupplementary circuit by corresponding semiconductor chips mounted on aprototyping board, and adding the generated circuit to a designverification target circuit to thereby generate an extended designverification target circuit, or generating an IOP-probing supplementaryHDL code, and adding it to a design verification target HDL code tothereby generated an extended design verification target HDL code;implementing the extended design verification target circuit or theextended design verification target HDL code in a correspondingsemiconductor chip on the prototyping board; performing a circuitverification process in a normal mode; inspecting whether probing isnecessary and whether it is an output probing; generating an inputprobing data by a server computer, switching to an input probing mode,applying the input probing data to the input probing line through aninput/output probing interface module by the server computer, andperforming input probing; and switching to an output probing mode,performing output probing, transferring the value obtained in an outputprobing line to the server computer through the input/output probinginterface module, to complete output probing.
 23. The method accordingto claim 22, wherein the input/output probing system controller forperforming input/output probing in the prototyping board connected withthe input/output probing interface module, the input/output probingserver computer and the simulation server computer performing thesimulator are connected, or the input/output probing system controllerfor performing input/output probing in the prototyping board connectedwith the input/output probing interface module, an input/output probingserver computer and the simulation accelerator server computer areconnected through a local or remote area computer network or through aninter-network, so that emulation and simulation are performed in aremote manner in a dispersed network environment on the basis of theinput/output probing method using the input/output probing apparatus.24. The Internet-based semiconductor design verifying and inspectingmethod according to claim 23, wherein the mixed emulation and simulationservice performed in a remote manner in the dispersed networkenvironment is provided on the Internet.
 25. The method according toclaim 24, wherein the mixed emulation and simulation service performedin a remote manner in the dispersed network environment is provided onthe Internet on the basis of the input/output probing method using theIOP-probing supplementary circuit.